Definitions
The term "interconnect" is herein defined to mean the circuitry and data paths between a data processor and the memory resources used by the data processor. The interconnect may also connect a data processor to various input/output channels as well as to memory resources.
The term "strongly ordered," as in "strongly ordered transactions," is herein defined to mean that transactions must be executed in the same order as specified in the program instruction stream.
The term "performing memory transactions in parallel" refers to the fact that in many computer system some memory transactions can be performed in parallel, during overlapping time periods, using parallel memory transaction paths available in the interconnect.
The term "parallelism" in the context of this document refers to the performance of memory transactions in parallel, during overlapping time periods, using parallel memory transaction paths available in the interconnect; it does not refer to the parallel execution of instructions by a data processor except to the extent that programs instructions are incidentally performed in parallel via the parallel execution of their associated memory transactions.
A memory transaction is one of the following:
Store: a request by a processor to replace the value of a specified memory location. The address and new value are bound to the store transaction when the processor initiates the store transaction. A store is complete when the new value is visible to all processors in the system (globally visible). PA1 Load: a request by a processor to retrieve the value of a specified memory location. The address is bound to the load transaction when the processor initiates the load transaction. A load is complete when the value being returned cannot be modified by a store made by another processor. PA1 Atomic: a load/store pair with the guarantee that no other memory transaction will alter the state of the memory between the load and the store. An atomic transaction is considered to be both a load and a store. PA1 Flush: a request by a processor to force changes in the data space aliased to the instruction space to be consistent. Flush transactions are considered to be store operations for memory model purposes. PA1 Interrupt: a cross-call transaction from one processor directly to another processor. Interrupt transactions are considered to be like store operations for memory model purposes. PA1 Prefetch: is considered to be a load operation for the memory model purposes. PA1 RMO (relaxed memory order). In programs and program segments using RMO, there are no ordering restrictions on any transaction issued to the interconnect beyond those required for processor self-consistency. PA1 PSO (partial store order). In programs and program segments using PSO, loads are blocking with respect to all subsequent memory transactions and are ordered with respect to earlier loads. Atomic transactions are ordered with respect to load transactions (i.e., atomic transactions and load transactions cannot bypass each other). Stores can bypass other stores, but a later store cannot bypass an earlier a load transaction. From another viewpoint, the specification for PSO is that of RMO with the additional requirement that all memory transactions with load semantics (including loads and atomic transactions) are followed by an implied Membar LoadLoad LoadStore. PA1 TSO (total store order). In programs and program segments using TSO, stores do not bypass stores, and loads are blocking to subsequent stores and loads and do not bypass loads. Stores must not bypass prior loads, although loads may bypass prior stores. Atomic transactions are blocking to subsequent transactions. From another viewpoint, the specification for TSO is that of PSO with the additional requirement that all memory transactions with store semantics (including stores and atomic transactions) are followed by an implied Membar StoreStore. PA1 SSO (strong sequential order). SSO is normally required for accessing I/O devices. SSO is also used in programs that assume sequentially consistent hardware. The transaction issue order, completion order, and program order, are all the same. Loads and stores in program order do not bypass each other either in the processor or in the interconnect. PA1 membar memsync: all memory transaction instructions (of all types) before this membar instruction must be completed prior to execution of any memory transaction instructions after this membar instruction. PA1 membar store-store: all store instructions before this membar instruction must be completed prior to execution of any store instructions after this membar instruction. PA1 membar load-load: all load instructions before this membar instruction must be completed prior to execution of any load instructions after this membar instruction. PA1 membar store-load: all store instructions before this membar instruction must be completed prior to execution of any load instructions after this membar instruction. PA1 membar load-store: all load instructions before this membar instruction must be completed prior to execution of any store instructions after this membar instruction.
"Program order" is a per-processor order that denotes the sequence in which processor n logically executed instructions. Memory transactions A and B are said to be in program order if and only if memory transaction A is caused by an instruction that is executed before the instruction that caused memory transaction B.
The term "memory transaction ordering model," usually shortened for conciseness to "memory model," is herein defined to mean a set of rules that define the extent to which memory transactions may be executed in a different order from the order in which they were generated. The following are definitions of four memory models from the point of view of the interconnect.
The terms "synchronization commands" and "membar" instructions both refer to instructions used for ensuring that some or all types of memory transactions prior a synchronization point are completed before execution of the memory transactions after the synchronization point. For the purposes of this document, five types of membar instructions are defined:
When using the RMO model, any ordering requirements between two transactions are enforced by issuing the appropriate membar instruction(s). When using the TSO model, load transactions are implicitly followed by a "membar load-load" instruction and a "membar load-store" instruction, and store transactions are implicitly followed by a "membar store-store" instruction.